module REG_IF_ID(
    input clk,
    input rst_n,
    input stall,
    input flush,
    
    input [31:0] pc_in,
    input [31:0] pc4_in,
    input [31:0] inst_in,
    
    output reg [31:0] pc_out,
    output reg [31:0] pc4_out,
    output reg [31:0] inst_out
    );
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      pc_out <= 32'b0;
        else if(flush)  pc_out <= 32'b0;
        else if(stall)  pc_out <= pc_out;
        else            pc_out <= pc_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      pc4_out <= 32'b0;
        else if(flush)  pc4_out <= 32'b0;
        else if(stall)  pc4_out <= pc4_out;
        else            pc4_out <= pc4_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      inst_out <= 32'b0;
        else if(flush)  inst_out <= 32'b0;
        else if(stall)  inst_out <= inst_out;
        else            inst_out <= inst_in;
    end
    

endmodule
